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UVM is a standardized methodology for verifying complex IP and SOC in the semiconductor industry. UVM is an Accellera standard and developed with support from multiple vendors Aldec, Cadence, Mentor, and Synopsys.
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UVM is a standardized methodology for verifying complex IP and SOC in the semiconductor industry. UVM is an Accellera standard and developed with support from multiple vendors Aldec, Cadence, Mentor, and Synopsys.UVM 1.0 was released on 28 Feb 2011 which was widely accepted by verification enginees across the world. UVM has evolved and undergone a series of minor releases, which introduced new features.
UVM provides the standard structure for creating test-bench and UVCs. The following features are provided by UVM
- Separation of tests from test bench
- Transaction-level communication (TLM)
- Sequences
- Factory and configuration
- Message reporting
- End-of-test mechanism
- Register layer
The main advantages of adopting UVM methodology are
- Reusability through test bench re‐use and verification IP allowing plug and play
- A proven methodology with industry wide support and availability of engineers with existing knowledge/experience
- Simulator and vendor independence
