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To verify an RTL design, you must define a stimulus (i.e. what kind of data should be sent to the DUT). In any test-bench environment, the driver is responsible for signal activities at the bit level. SystemVerilog in functional verification provide this abstraction.
It introduces the concept of TRANSACTION, GENERATOR and CHANNEL. Transaction is the actual data item which is generated by the Generator. It is sent to the driver through the Channel to drive it on the DUT interface.
For many years, engineers have been trying to standardize the Test- Bench architecture. Engineers have come with methodologies like OVM, VMM and UVM. In the following presentation we explain how UVM structures the Transaction, Generator and Channel. IN UVM, Transaction is named as Sequence ITEM, Generator as Sequence and Channel as Sequencer.
To get the basic understanding of the UVM Methodology refer to basic UVM Tutorial.
Author: Chandra Bhushan Singh
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